A variety of techniques are used to stack packaged integrated circuits. Some methods require special packages, while other techniques stack packages configured to allow stand-alone deployment in an operating environment.
“Chip scale packaging” or CSP refers generally to packages that provide connection to an integrated circuit through a set of contacts (often embodied as “bumps” or “balls”) arrayed across a major surface of the package. Instead of leads emergent from a peripheral side of the package as in “leaded” packages, in a CSP, contacts are placed on a major surface and typically emerge from the planar bottom surface of the package. The absence of “leads” on package sides renders most stacking techniques devised for leaded packages inapplicable for CSP stacking.
CSP has enabled reductions in size and weight parameters for many applications. CSP is a broad category including a variety of packages from near chip scale to die-sized packages such as the die sized ball grid array (DSBGA). To meet the continuing demands for cost and form factor reductions concurrent with increasing capabilities and capacities, technologies that aggregate plural integrated circuit dies in a package been developed. The techniques and technology for stacking plural integrated circuit dies within a single package, however, are not generally applicable for stacking packages that are configured to allow stand-alone deployment in an operating environment.
There are several known techniques for stacking integrated circuit packages articulated in chip scale technology. A variety of previous techniques for stacking CSPs typically present complex structural arrangements and thermal or high frequency performance issues. For example, thermal performance is a characteristic of importance in CSP stacks. With increasing operating frequencies of most systems, high frequency performance issues are also increasingly important. Further, many stacking techniques result in modules that exhibit profiles taller than may be preferred for particular applications.
Staktek Group L.P., the assignee of the present invention, has developed a variety of stacked module designs that employ a form standard or mandrel that can provide thermal and/or construction advantages while providing a standard form that may allow use of a flexible circuit design with a variety of CSP types and body sizes. The mandrel or form standard stack designs come in a variety of shapes and sizes and materials. Some form standards extend beyond the perimeter edge or the extent of the CSP body and thus provide a form about which the flex circuitry transits. Some other form standards are substantially planar and have a lateral extent smaller than the lateral extent of an adjacent CSP. Although form standards provide numerous benefits in stacked module designs, the use of form standards may add various cost and complexity issues to the design and manufacturing issues inherent with stacked modules.
Stacked module design and assembly techniques and systems that provide a thermally efficient, reliable structure that perform well at higher frequencies but do not add excessive height to the stack that can be manufactured at reasonable cost with readily understood and managed materials and methods are provided.